---
product_id: 267247010
title: "CREATESPACE RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design"
price: "£129.28"
currency: GBP
in_stock: true
url: https://www.desertcart.co.uk/products/267247010-createspace-rtl-modeling-with-systemverilog-for-simulation-and-synthesis-using
store_origin: GB
region: United Kingdom
---

# CREATESPACE RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

**Price:** £129.28
**Availability:** ✅ In Stock

## Quick Answers

- **What is this?** CREATESPACE RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
- **How much does it cost?** £129.28 with free shipping
- **Is it available?** Yes, in stock and ready to ship
- **Where can I buy it?** [www.desertcart.co.uk](https://www.desertcart.co.uk/products/267247010-createspace-rtl-modeling-with-systemverilog-for-simulation-and-synthesis-using)

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- Customers looking for quality international products

## Why This Product

- Free international shipping included
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## Description

CREATESPACE RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

## Technical Specifications

| Specification | Value |
|---------------|-------|
| Best Sellers Rank | #304,864 in Books ( See Top 100 in Books ) #28 in Digital Design (Books) #9,793 in Textbooks (Special Features Stores) |
| Customer Reviews | 4.8 4.8 out of 5 stars (49) |
| Dimensions  | 6 x 1.1 x 9 inches |
| ISBN-10  | 1546776346 |
| ISBN-13  | 978-1546776345 |
| Item Weight  | 1.42 pounds |
| Language  | English |
| Print length  | 488 pages |
| Publication date  | June 10, 2017 |
| Publisher  | CreateSpace Independent Publishing Platform |

## Images

![CREATESPACE RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design - Image 1](https://m.media-amazon.com/images/I/71nRlJ4QanL.jpg)

## Frequently Bought Together

- RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
- SystemVerilog for Verification
- The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology

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*Product available on Desertcart United Kingdom*
*Store origin: GB*
*Last updated: 2026-05-18*